Technical Field
The present invention relates to semiconductor devices and processes, and more particularly to semiconductor devices that employ doped ZnO with InGaAs metal oxide semiconductor devices to reduce contact resistance.
Description of the Related Art
Field effect transistors (FETs) which employ III-V materials, such as GaAs, InP or InGaAs substrates, often include a doped source and drain region made of a similar material. In one common structure, III-V FETs include source/drain (S/D) regions formed from doped InGaAs (e.g., n+ InGaAs). n+ InGaAs is not ideal for S/D regions. In InGaAs nFETs, the n+ InGaAs S/D regions suffer from a low doping concentration (e.g., 1×1019 cm−3). In addition, there is relatively high junction leakage and high contact resistance in InGaAs S/D regions. Further, the formation process requires patterned implantation of n+ dopants, which adds time and expense to the process, and may result in junction damage.
These III-V FET structures often include metal contacts on the n+ InGaAs S/D regions. The metal contacts may include Ti, Pd, Au or Ni, and have a contact resistance (resistivity) that exceeds 5×10−8 Ohm-cm2. This significantly falls short of the desired contact resistance (resistivity) of less than 5×10−9 Ohm-cm2.